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1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
DESCRIPTION
The M5M5W816 is a family of low voltage 8-Mbit static RAMs organized as 524288-words by 16-bit, fabricated by Mitsubishi's high-performance 0.18m CMOS technology. The M5M5W816 is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. From the point of operating temperature, the family is divided into two versions; "Standard" and "I-version".
FEATURES
- Single 1.8~2.7V power supply - Small stand-by current: 0.1A (2.7V, typ.) - No clocks, No refresh - Data retention supply voltage =1.0V - All inputs and outputs are TTL compatible. - Easy memory expansion by S1, S2, BC1 and BC2 - Common Data I/O - Three-state outputs: OR-tie capability - OE prevents data contention in the I/O bus - Process technology: 0.18m CMOS - Package: 48ball 7.0mm x 8.5mm CSP
Version, Operating temperature Part name
M5M5W816WG -85L
Power Supply
1.8 ~ 2.7V 1.8 ~ 2.7V 1.8 ~ 2.7V 1.8 ~ 2.7V
Access time
max.
85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns
Stand-by current (Vcc=2.7V) Ratings (max.) * Typical 25C 40C 25C 40C 70C 85C 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 --1 --1 --2 --2 16 8 16 8 ----30 15
Active current Icc1 (2.7V, typ.) 40mA (10MHz) 5mA (1MHz)
Standard
0 ~ +70C
M5M5W816WG -10L M5M5W816WG -85H M5M5W816WG -10H M5M5W816WG -85LI
I-version
-40 ~ +85C
M5M5W816WG -10LI M5M5W816WG -85HI M5M5W816WG -10HI
* Typical parameter indicates the value for the center of distribution, and not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1 A B
BC1
2
OE
3
A0
4
A1
5
A2
6
S2
DQ9
BC2
A3
A4
S1
DQ1
Pin
Function
C DQ10 D E F G H
GND
DQ11
A5
A6
DQ2
DQ3
A0 ~ A18 Address input DQ1 ~ DQ16 Data input / output S1 S2 W OE BC1 BC2 Vcc GND Chip select input 1 Chip select input 2 Write control input Output enable input Lower Byte (DQ1 ~ 8) Upper Byte (DQ9 ~ 16) Power supply Ground supply
DQ12
A17
A7
DQ4
VCC
VCC
DQ13
GND
A16
DQ5
GND
DQ15
DQ14
A14
A15
DQ6
DQ7
DQ16
N.C.
A12
A13
W
DQ8
A18
A8
A9
A10
A11
N.C.
Outline: 48FHA NC: No Connection
MITSUBISHI ELECTRIC
1
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
FUNCTION
The M5M5W816WG is organized as 524288-words by 16bit. These devices operate on a single +1.8~2.7V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the function table. A write operation is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the low level S1 and the high level S2. The address(A0~A18) must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and S1 and S2 are in an active state(S1=L,S2=H). When setting BC1 at the high level and other pins are in an active stage , upper-byte are in a selectable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high level and other pins are in an active stage, lower-byte are in a selectable mode and upper-byte are in a non-selectable mode.
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
When setting BC1 and BC2 at a high level or S1 at a high level or S2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply current is reduced as low as 0.1A(25C, typical), and the memory data can be held at +1V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1 H L H X L L L L L L L L L S2 BC1 BC2 L XX L XX HXX XHH HL H HLH HLH HHL HHL HHL HL L HL L HL L W OE XX XX XX XX LX HL HH LX HL HH LX HL HH Mode
Non selection Non selection Non selection Non selection
DQ1~8
DQ9~16
Write Read Write Read Write Read
BLOCK DIAGRAM
A0 A1 MEMORY ARRAY 524288 WORDS x 16 BITS A17 A18 S1 S2 BC1 BC2 W
CLOCK GENERATOR
High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z
High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z
Icc Standby Standby Standby Standby Active Active Active Active Active Active Active Active Active
DQ 1
DQ 8
-
DQ 9
DQ 16
Vcc
GND OE
MITSUBISHI ELECTRIC
2
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C Standard I-version (-L, -H) (-LI, -HI)
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Ratings
Units
Vcc VI VO Pd Ta Tstg
-0.5* ~ +4.6 -0.2* ~ Vcc + 0.2 (max. 4.6V) 0 ~ Vcc 700 0 ~ +70 - 40 ~ +85 - 65 ~ +150
* -3.0V in case of AC (Pulse width < 30ns) =
V mW
C C
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=1.8 ~ 2.7V, unless otherwise noted) Limits Min 0.7 x Vcc Typ Max Vcc+0.2V Units
Parameter High-level input voltage Low-level input voltage
High-level output voltage
Conditions
VIH VIL VOH VOL II IO
Low-level output voltage Input leakage current Output leakage current ( AC,MOS level )
IOH= -0.1mA IOL=0.1mA VI =0 ~ Vcc
BC1 and BC2=VIHor S1=VIHor S2=VIL or OE=VIH, VI/O=0 ~ Vcc BC1 and BC2< 0.2V, S1< 0.2V, S2 Vcc-0.2V = = > other inputs < 0.2V or = Vcc-0.2V = Output - open (duty 100%)
-0.2 * 1.6
0.4 0.2 1 1 50 10 50 10 1 2 8 15 16 30 0.5
V
A
Icc1 Active supply current
f= 10MHz f= 1MHz f= 10MHz f= 1MHz ~ +25C
Active supply current Icc2 ( AC,TTL level )
BC1 and BC2=VIL , S=VIL ,S2=VIH other pins =VIH or VIL Output - open (duty 100%)
> (1) S1 = Vcc - 0.2V, > (2) S2 = 0.2V, other inputs = 0 ~ Vcc > (3) BC1 and BC2 = Vcc - 0.2V > S1 < 0.2V, S2 = Vcc - 0.2V = other inputs = 0 ~ Vcc
-
other inputs = 0 ~ Vcc
-H, -HI -HI -L, -LI -LI
~ +40C ~ +70C ~ +85C ~ +70C ~ +85C
Icc3 Stand by supply current
( AC,MOS level )
40 5 40 5 0.1 0.2 -
mA
A
Stand by supply current Icc4 ( AC,TTL level )
BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc
mA
< Note 1: Direction for current flowing into IC is indicated as positive (no mark) * -1.0V in case of AC (Pulse width = 30ns) Note 2: Typical parameter indicates the value for the center of distribution at 2.7V, and not 100% tested.
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions
(Vcc=1.8 ~ 2.7V, unless otherwise noted) Limits Typ Units
Min VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Max
CI CO
10 10
pF
MITSUBISHI ELECTRIC
3
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply voltage Input pulse Input rise time and fall time Reference level Output loads
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=1.8 ~ 2.7V, unless otherwise noted)
1.8~2.7V VIH=0.7 x Vcc, VIL=0.2V 5ns VOH=VOL=0.9V
Transition is measured 200mV from steady state voltage.(for ten,tdis)
1TTL DQ CL
Including scope and jig capacitance
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR Parameter Read cycle time Address access time Chip select 1 access time Chip select 2 access time Byte control 1 access time Byte control 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after BC1 high Output disable time after BC2 high Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after BC1 low Output enable time after BC2 low Output enable time after OE low Data valid time after address
85L, 85H, 85LI, 85HI 10L, 10H, 10LI, 10HI
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min 85
Max 85 85 85 85 85 45 30 30 30 30 30
Min 100
Max 100 100 100 100 100 50 35 35 35 35 35
ta(A) ta(S1) ta(S2) ta(BC1) ta(BC2) ta(OE) tdis(S1) tdis(S2) tdis(BC1) tdis(BC2) tdis(OE) ten(S1) ten(S2) tdis(BC1) tdis(BC2) ten(OE) tV(A)
10 10 10 10 5 10
10 10 10 10 5 10
(3) WRITE CYCLE
Limits Symbol Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Byte control 1 setup time Byte control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low
85L, 85H, 85LI, 85HI 10L, 10H, 10LI, 10HI
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
Min 85 60 0 70 70 70 70 70 45 0 0
Max
Min 100 75 0 85 85 85 85 85 50 0 0
Max
30 30 5 5 5 5
35 35
MITSUBISHI ELECTRIC
4
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
(4)TIMING DIAGRAMS Read cycle
A0~18 ta(A) ta(BC1) or ta(BC2) BC1,BC2
(Note3)
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCR tv (A)
tdis (BC1) or tdis (BC1) ta(S1)
(Note3)
S1
(Note3)
tdis (S1) ta(S2)
(Note3)
S2
(Note3)
tdis (S2) ta (OE)
(Note3)
OE
(Note3) W = "H" level
ten (OE) ten (BC1) ten (BC2) ten (S1) ten (S2) tCW
tdis (OE)
(Note3)
DQ1~16
VALID DATA
Write cycle ( W control mode )
A0~18
tsu (BC1) or tsu(BC2) BC1,BC2
(Note3) (Note3)
S1
(Note3)
tsu (S1)
(Note3)
S2
(Note3)
tsu (S2)
(Note3)
OE tsu (A) W tdis(OE) DQ1~16
tsu (A-WH) tw (W) tdis (W)
trec (W) ten(OE) ten (W)
DATA IN STABLE
tsu (D)
th (D)
MITSUBISHI ELECTRIC
5
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
Write cycle (BC control mode)
A0~18 tsu (A) BC1,BC2 S1
(Note3)
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCW
tsu (BC1) or tsu (BC2)
trec (W)
(Note3)
S2
(Note3) (Note5) (Note4) (Note3) (Note3) (Note3)
W
tsu (D) DQ1~16
DATA IN STABLE
th (D)
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high overlaps BC1 and/or BC2 low and W low. Note 5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
MITSUBISHI ELECTRIC
6
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
Write cycle (S1 control mode)
A0~18 tCW
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
BC1,BC2
(Note3)
tsu (A)
tsu (S1)
trec (W)
(Note3)
S1
S2
(Note3) (Note5) (Note3)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Write cycle (S2 control mode)
A0~18
tCW
BC1,BC2
(Note3)
tsu (A)
tsu (S2)
trec (W)
(Note3)
S1
S2
(Note3) (Note5) (Note3)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
MITSUBISHI ELECTRIC
7
1999.1.15
Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Min
Limits Typ
Max
Units V
Vcc (PD) Power down supply voltage VI (BC) VI (S1) VI (S2)
Byte control input BC1 & BC2
1.0
1.8V 1.0V 1.8V Vcc(PD) Vcc(PD) 1.8V Vcc(PD) Vcc(PD) 1.8V
0.7xVcc Vcc(PD) 0.7xVcc Vcc(PD) ~ +25C ~ +40C ~ +70C ~ +85C ~ +70C ~ +85C V V
Chip select input S1 Chip select input S2
1.0V
Vcc=1.0V
> (1) S1 = Vcc - 0.2V,
Icc (PD)
Power down supply current
other inputs = 0 ~ Vcc other inputs = 0 ~ Vcc
-H, -HI -HI -L, -LI -LI
> (2) S2 = 0.2V, > (3) BC1 and BC2 = Vcc - 0.2V > S1 < 0.2V, S2 = Vcc - 0.2V = other inputs = 0 ~ Vcc
-
0.02 0.05 -
0.2 0.5 1 4 7.5 8 15
A
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time Power down recovery time
Note 2: Typical parameter of Icc(PD) indicates the value for the center of distribution at 1.0V, and not 100% tested.
Limits Test conditions Min Typ Max
Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC control mode Vcc tsu (PD) 0.7 x Vcc BC1 BC2 S1 control mode Vcc tsu (PD) 0.7 x Vcc S1 S2 control mode Vcc S2 Vcc-0.2V tsu (PD) 1.8V S1 > Vcc-0.2V = 1.8V 1.8V trec (PD) 0.7 x Vcc BC1 , BC2 >Vcc-0.2V = 1.8V 1.8V trec (PD) 0.7 x Vcc
1.8V
trec (PD) 0.7 x Vcc
S2
0.2V 8
MITSUBISHI ELECTRIC

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